Integrated Circuit Assembly and Method of Making

ABSTRACT

An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.14/572,580, filed Dec. 16, 2014 which, in turn, is a continuation ofSer. No. 13/725,306, filed Dec. 21, 2012, now U.S. Pat. No. 8,912,646,which, in turn, is a continuation-in-part of U.S. patent applicationSer. No. 13/459,110, filed Apr. 28, 2012, now U.S. Pat. No. 8,357,975,which, in turn, is a continuation of U.S. patent application Ser. No.12/836,506 filed Jul. 14, 2010, now U.S. Pat. No. 8,232,597, whichclaims the benefit of U.S. Provisional Patent No. 61/225,914 filed Jul.15, 2009. The content of U.S. Provisional Patent No. 61/225,914, U.S.Pat. No. 8,232,597, U.S. Pat. No. 8,357,975, U.S. Pat. No. 8,912,646 andU.S. patent application Ser. No. 14/572,580 are is incorporated hereinby reference.

This application is related to Stuber et al., U.S. patent applicationSer. No. 13/725,403, filed on Dec. 21, 2012 and titled: “Back-to-backedstacked integrated circuit assembly and method of making”, and to Stuberet al., U.S. patent application Ser. No. 13/725,245, filed on Dec. 21,2012 and titled: “Thin integrated circuit chip-on-board assembly andmethod of making”, now U.S. Pat. No. 8,921,168, both owned by theassignee of the present application and hereby incorporated byreference.

FIELD OF THE INVENTION

The invention described relates to integrated circuit devices andprocessing generally, and more specifically to packaging and assemblingintegrated circuits into systems.

BACKGROUND OF THE INVENTION

Semiconductor-on-insulator (SOI) technology was first commercialized inthe late 1990s. The defining characteristic of SOI technology is thatthe semiconductor region in which circuitry is formed is isolated frombulk substrate by an electrically insulating layer. This insulatinglayer is typically silicon-dioxide. The reason silicon-dioxide is chosenis that it can be formed on a wafer of silicon by oxidizing the waferand is therefore amenable to efficient manufacturing. The advantageousaspects of SOI technology stem directly from the ability of theinsulator layer to electronically isolate the active layer from bulksubstrate. As used herein and in the appended claims, the region inwhich signal-processing circuitry is formed on an SOI structure isreferred to as the active layer of the SOI structure. The term “activelayer” is also used herein, and in the appended claims, to refer to anyregion of circuitry formed on any substrate. For example, an activelayer may contain both active and passive devices. Moreover, thecircuitry referred to by the term “active layer” need not contain anyactive devices; rather, such a layer may contain only passive devices.Examples of such passive circuits include bandpass filters and resistordividers.

SOI technology represents an improvement over traditional bulk substratetechnology because the introduction of the insulating layer isolates theactive devices in an SOI structure which improves their electricalcharacteristics. For example, the threshold voltage of a transistor isdesirously uniform, and is set in large part by the characteristics ofthe semiconductor material underneath the transistor's gate. If thisregion of material is isolated, there is less of a chance that furtherprocessing will affect this region and alter the threshold voltage ofthe device. Additional electrical characteristic improvements stemmingfrom the use of the SOI structure include fewer short channel effects,decreased capacitance for higher speed, and lower insertion loss if thedevice is acting as a switch. In addition, the insulating layer can actto shield the active devices from harmful radiation. This isparticularly important for integrated circuits that are used in spacegiven the prevalence of harmful ionizing radiation outside the earth'satmosphere.

SOI wafer 100 is shown in FIG. 1. The wafer includes substrate,insulator layer 102, and active layer 103. The substrate is typically asemiconductor material such as silicon. Insulator layer 102 is adielectric which is often silicon-dioxide formed through the oxidationof substrate layer 101. Active layer 103 includes a combination ofdopants, dielectrics, polysilicon, metal layers, passivation, and otherlayers that are present after circuitry 104 has been formed therein.Circuitry 104 may include metal wiring; passive devices such asresistors, capacitors, and inductors; and active devices such astransistors. As used herein and in the appended claims, the “top” of SOIwafer 100 references top surface 105 while the “bottom” of SOI wafer 100references bottom surface 106. This orientation scheme persistsregardless of the relative orientation of SOI wafer 100 to other framesof reference, and the removal of layers from, or the addition of layersto SOI wafer 100. Therefore, active layer 103 is always “above”insulator layer 102. In addition, a vector originating in the center ofactive layer 103 and extending towards bottom surface 106 will alwayspoint in the direction of the “back side” of the SOI structureregardless of the relative orientation of SOI wafer 100 to other framesof references, and the removal of layers from, or the addition of layersto SOI wafer 100.

Semiconductor devices can be subject to a phenomenon known as thefloating-body effect. Semiconductor-on-insulator devices areparticularly susceptible to this effect. The manner in which thefloating-body effect is exhibited by an n-type field effect transistor(NFET) will be described for illustrative purposes, but thefloating-body effect is exhibited by many other active devices. FIG. 1Bdisplays a side-view of NFET 108. NFET 108 is an SOI device, and istherefore disposed above insulator layer 102. The floating-body effectis caused by the presence of excess carriers in body 109. Carriers canbuild up in body 109 through random generation of electron and holepairs by thermal or optical means, through scattering of high speedelectrons in channel 110, through leakage from source 111 or drain 112,through band-to-band tunneling, or through avalanche breakdown inchannel 110. The presence of excess carriers is therefore inevitable inany semiconductor device. However, in an SOI device, body 109 isisolated and limited as compared to a device whose body is part of bulksubstrate. Therefore, far fewer excess carriers are needed to alter thecharacteristics of the active device.

Two alterations to the characteristics of an active device caused by thefloating-body effect that are exacerbated by an SOI structure are thekink effect, and the non-linear capacitance exhibited by an activedevice that is in an off state. The introduction of excess carriers tobody 109 due to avalanche breakdown caused by a high potential appliedacross source 111 and drain 112 will have the effect of greatlyincreasing the current through channel 110. The effect is called thekink effect because the relatively flat portion on a curve of thechannel current against the drain-source potential will have a kinkupwards at the point where this effect takes hold. The relatively flatportion of the curve is located in a region where the current is—forsome applications—desirously set predominately by the voltage at gate113. This effect can therefore be problematic because certain analogcircuit applications are dependent upon the current of an active devicebeing independent of the drain-source potential when operating in thisregion.

In contrast to the kink effect, the non-linearity of a device'soff-state capacitances is not caused by avalanche breakdown. Instead,carriers build up through other less aggressive means as describedabove. If the potential of body 109 shifts to a significant enoughdegree, the capacitance seen by a signal at drain 112 will change in anon-linear fashion. The change will be non-linear because the excesscarriers will build up in body 109 over time making the capacitancetime-variant. Also, the charge build up will make the capacitance of thejunction between body 109 and drain 112 dependent upon the signal atdrain 112 which is also a characteristic of a non-linear system. Thiseffect can be problematic because certain circuit designs are dependentupon the retention of a highly linear characteristic for their processedsignals. For example, if NFET 108 was being used as a switch in aradio-frequency (RF) application wherein it had to be in an off statewhile a signal was transmitted on a line connected to drain 112, thecapacitance from drain 112 to body 109 would have to be linear in orderto prevent the production of unwanted harmonic distortion andinter-modulation distortion in the signal.

A common solution to the floating-body effect in SOI devices includesthe introduction of a connection from body 109 to source 111. Thissolution is a subset of the more general family of solutions involvingthe use of what is called a “body tie”, or “body contact”. A bodycontact provides a connection to body 109 which serves to remove excesscarriers. The particular solution of connecting body 109 to source 111is employed most commonly because it is so simple. Unwanted charge thatbuilds up in body 109 will be able to escape from body 109 to source111, and will therefore not cause the kink effect or lead to theproduction of a non-linear capacitance.

Another solution to the floating-body effect in SOI devices involves theuse of a smart body tie. A smart body tie is a body tie that changes itsstate based on the state of the device for which it is providing a tie.An example of a smart body tie can be described with reference to FIG.1C. FIG. 1C comprises an NFET 114. The source of NFET 114 is connectedto ground 115. The drain of NFET 114 is connected to drain contact 116.The gate of NFET 114 is connected to gate contact 117, and the cathodeof diode 118. The body of NFET 114 is connected to the anode of diode118. A similar configuration could function by replacing NFET 114 with aPFET and reversing the polarity of diode 118. This structure isadvantageous in certain situations because the body tie formed by diode118 will conduct much more when the device is off as compared to whenthe device is on. This can be very helpful for the situation describedabove wherein a non-linear off-state capacitance of the FET would imbuea processed signal on drain contact 116 with distortion. When gatecontact 117 is low and the device is off, current will flow from thebody of NFET 114 to gate contact 117 through diode 118. However, whengate contact 117 is high, the path from the body to gate willeffectively be cut off. This can be highly advantageous given that thekink effect provides a benefit from the perspective of providing highercurrent during the device's on-state current. Therefore, this structureallows for the drawbacks of the floating body effect in one applicationto be eliminated while preserving the advantages of the floating bodyeffect.

Although these approaches have advantageous aspects in that they areable to remove excess charge from the body of an active device, they areat the same time slightly problematic because they generally requireanother layer of processing in close contact to the active devices. Thisadditional processing can complicate the fabrication process and cangenerally lead to non-idealities in the fabricated active devicesthrough manufacturing errors. In addition, these approaches requireadditional area on the active wafer which increases the cost of theoverall design. These approaches also suffer from the disadvantage ofhigh resistance along the width of the transistor from the body tie tothe most remote portion of the channel. High resistance can reduce theefficacy of the body tie in reducing floating body effects. Finally,these approaches may introduce parasitic capacitance to nodes of thedevice that will limit the speed of any circuit utilizing such a device.

Additionally, because of their unique structure,semiconductor-on-insulator integrated circuit chips offer opportunitiesto fit more electronic functions into smaller packages. Integratedcircuit chips are typically attached to printed circuit boards. Theseboards contain one or more layers of metal traces and vias, providingelectrical connections to chips and other components, thus completingthe electronic system. By using innovative ways of attaching theircomponent chips, boards can be made smaller in order to fit into smallerdevices.

Integrated circuit chips can be attached to printed circuit boards inseveral ways. Often they are mounted in packages that have variousconfigurations of pins, which, in turn, are inserted into holes in theprinted circuit boards and fixed in place. For a smaller outline, thepackaging step can be omitted, and the chip can be mounted directly onthe board. A common chip mounting technique—for mounting chips both inpackages and directly on boards—is wire bonding. In this method, thinwires connect pads in the package, or on the board, to pads on the chip.Usually, these bonding pads lie along the outside edges of the uppersurface of the chip.

Since the board area needed for a wire-bonded chip exceeds the chip areaby the length of the wires, other methods are available to replace wirebonding. In a second method, known as flip-chip or C4 (for controlledcollapse chip connection), bond pads on the chip are coated with solderbumps, and the chip is mounted face down on the board. In this method,the footprint on the board used by the chip is no larger than the areaof the chip. Eliminating the long wires may have performance advantagesas well.

Another method of reducing board size is to stack chips on top of eachother, while still being electrically connected to the board. Designersoften find it advantageous to stack related chips—for example, a memorychip and its controller. In this case, the upper chip is usuallyconnected directly to lower chip, and not necessarily to the board. Sucha stacked chip assembly will typically require a vertical connection,such as a through-silicon via, to route signals and/or power to at leastone of the chips. Such vertical connections, though expensive, canresult in substantial package size reductions, especially if thistechnique is combined with flip-chip mounting. In these assemblies, bothchips are either upside down, with C4 bumps formed on the lower chip; orthey are mounted face-to-face, with the C4 bumps formed directly onvertical connectors.

In some cases, chip stacking may be beneficial but vertical connectionsare not required. For example, multiple identical memory chips may beconnected to one controller chip, so as to increase memory capacity. Inthis case, the memory chips could be stacked and bonded individually tothe printed circuit board, connecting them to the nearby controllerchip. In these cases, both chips are typically mounted right side up,and both are wire bonded to the board. However, some of the area savingsafforded by chip stacking is lost due to the area consumed by themultitude of wire bonds.

Thus, there is an increasing need to produce small, complex circuitboards in a cost-efficient manner.

SUMMARY OF THE INVENTION

In one embodiment, an integrated circuit assembly includes an insulatinglayer having a having a first surface and a second surface. A firstactive layer contacts the first surface of the insulating layer. A metalbond pad is electrically connected to the first active layer and formedon the second surface of the insulating layer. A substrate having afirst surface and a second surface, with a second active layer formed inthe first surface, is provided such that the first active layer iscoupled to the second surface of the substrate.

In another embodiment, a method of fabricating an integrated circuitassembly includes providing a semiconductor-on-insulator that includesan insulating layer with a first surface and a second surface. A firstactive layer contacts the first surface of the insulating layer. Ahandle layer contacts the second surface of the insulating layer. Asubstrate having a first surface and a second surface is provided. Asecond active layer is formed on the first surface of the substrate. Thefirst active layer is coupled to the second surface of the substrate.The handle layer is removed, and a metal bond pad, electricallyconnected to the first active layer, is formed on the second surface ofthe insulating layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate a block diagram of an SOI device that issusceptible to the floating-body effect that is in accordance with theprior art.

FIG. 1C illustrates a block diagram of an NFET with a smart body contactthat is in accordance with the prior art.

FIG. 2 illustrates a block diagram of an SOI structure with a back sidebody contact that is in accordance with the present invention.

FIG. 3 illustrates a block diagram of an SOI structure with a back sidebody contact coupled to a gate through a pn-junction diode that is inaccordance with the present invention.

FIG. 4 illustrates a block diagram of an SOI structure with a back sidebody contact coupled to a gate through a hot-carrier-junction diode thatis in accordance with the present invention.

FIG. 5 illustrates a block diagram of the back side of an SOI structurehaving large polysilicon contact pads that is in accordance with thepresent invention.

FIG. 6 illustrates a process flow chart of a method of fabricating anintegrated circuit having a back side body contact that is in accordancewith the present invention.

FIG. 7 illustrates a block diagram of an SOI structure that is inaccordance with the present invention.

FIG. 8 is a flowchart of an exemplary method for forming a back-to-backstacked bulk integrated circuit.

FIGS. 9a-9i illustrate cross-sectional views of stages of forming aback-to-back stacked integrated circuit according to some embodiments.

FIG. 10 is a cross-sectional view of another embodiment of aback-to-back stacked integrated circuit.

FIGS. 11a-11b are cross-sectional views of another embodiment of aback-to-back stacked integrated circuit.

FIGS. 12a-12b are cross-sectional views of another embodiment of aback-to-back stacked integrated circuit, wherein a third integratedcircuit is stacked on top of the back-to-back integrated circuitassembly.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Reference now will be made in detail to embodiments of the disclosedinvention, one or more examples of which are illustrated in theaccompanying drawings. Each example is provided by way of explanation ofthe present technology, not as a limitation of the present technology.In fact, it will be apparent to those skilled in the art thatmodifications and variations can be made in the present technologywithout departing from the spirit and scope thereof. For instance,features illustrated or described as part of one embodiment may be usedwith another embodiment to yield a still further embodiment. Thus, it isintended that the present subject matter covers such modifications andvariations as are within the scope of the appended claims and theirequivalents.

Embodiments of the present invention provide for the production of SOIdevices that have space-saving efficient back side body contacts.Embodiments of the invention achieve this result through the utilizationof back side processing, the removal of portions of the SOI buriedinsulator layer, and the deposition of an electrically conductivematerial which connects a body contact of an active device to a secondcontact located in the same active layer as the active device itself.

Embodiments of the present invention also provide for an integratedcircuit assembly including a semiconductor-on-insulator (SOI) coupled tothe back surface of a substrate having an active layer formed on itsfront surface. The active layer of the SOI faces the back surface of thesubstrate, and pads are formed on the exposed insulator so as toelectrically contact the SOI's active layer. Embodiments of the presentinvention also include methods of fabricating such an integrated circuitassembly. These methods include providing an SOI with an insulatorinterposed between an active layer and a handle layer, coupling theactive layer to the back of a substrate having a second active layer onits front, removing the handle layer from the SOI, and forming a metalbond pad electrically contacting the SOI's active layer on the exposedinsulator surface.

FIG. 2 displays SOI structure 200 which is in accordance with thepresent invention. As with prior art SOI devices, active layer 103 isabove insulator layer 102. Electrically conductive layer 201 is belowinsulator layer 102, and is disposed on the back side of insulator layer102 such that it fills excavated insulator region 202. As seen in thefigure, insulator layer 102 is at least partially vertically coextensivewith electrically conductive layer 201 in excavated insulator region202. As used herein and in the appended claims, the term “region” is notmeant to be limited to the description of a single contiguous region.Excavated insulator region 202 therefore allows for separate physicalcontacts between the body 109 of active device 203 and electricallyconductive layer 201 at body contact 204, and between said electricallyconductive layer 201 and said active layer 103 at second contact 205.Active layer 103 is bonded to handle wafer 206 to provide support toactive layer 103 while it is being processed. However, handle wafer 206can be removed at a later time during processing. In addition, stabilityduring processing may be provided by other means such that handle wafer206 does not need to be attached at all.

Embodiments of the present invention which are described with referenceto FIG. 2 in the previous paragraph function to remove excess carriersfrom body 109 to alleviate the floating body effect for active device203. Excess carriers that build up in body 109 are able to flow outthrough electrically conductive layer 201 and back into active layer103. Handle wafer 206 allows for the processing of the SOI structurefrom the back side which enables easy access to the body of activedevice 203. Advantageously, active device 203 can be formed in activelayer 103 unimpeded by the need for body tie circuitry. As such, thebody tie circuitry is much less likely to adversely affect the finishedactive devices or hinder the flexibility of a designer that develops thelayout for the active devices. In addition, any parasitic capacitancethat results from having body tie circuitry close by can be greatlyalleviated because only a small contact is needed near the body of thedevice.

A specific embodiment of the present invention can be described withreference again to FIG. 2. In FIG. 2, a circuit branch comprising bothbody contact 204 and second contact 205 connects to both source 111 ofactive device 203, and body 109 of active device 203. In specificembodiments of the invention, the configuration shown in FIG. 2 allowsexcess carriers to flow to source 111 and then away from active device203 along the source electrode. This is a convenient configuration giventhat the source of NFETs will generally be at a lower potential thanbody 109 so p-type carriers will flow out through this circuit branch.In addition, the source of a p-type field effect transistor (PFET) willgenerally be at a higher potential than body 109 so n-type carriers willflow out through this circuit branch. Another specific embodiment of thepresent invention comprises a circuit branch comprising both bodycontact 204 and second contact 205. However, in contrast to theconfiguration shown in FIG. 2, the circuit branch that includes bodycontact 204 and second contact 205 connects gate 113 to body 109. Theresultant device is commonly referred to as a dynamic-threshold FET(DTFET or DTMOS). This configuration will function by providing a pathfor carriers to leave body 205 as they will be attracted to the signalsource for gate 210. The DTMOS device provides higher threshold voltagewhen the transistor is biased in the OFF condition and lower thresholdvoltage when the device is in the ON condition. This advantageouslyprovides low leakage when OFF and high drive strength when it is turnedON.

The back side processing concepts discussed above with reference to FIG.2 can be applied to the formation of smart body contacts to formstructures that are in accordance with the present invention. Inspecific embodiments of the present invention, a variable impedancecircuit branch comprising body contact 204 and second contact 205 isconfigured to have a high impedance when active device 203 is in an onstate, and a low impedance when active device 203 is not in an on state.Although these embodiments are described below with reference to NFETdevices the same result can be achieved by using a PFET device in placeof the described NFET device while also configuring any attached diodesto have opposite polarity.

An SOI structure 300 that is in accordance with the present inventioncan be described with reference to FIG. 3. In FIG. 3, gate 113 iscoupled to electrically conductive layer 201 through a diode comprisinganode 302 and cathode 301. In specific embodiments of the invention,anode 302 will comprise a region of active layer 103 that has been dopedmore using the same doping profile as body 109. In specific embodimentsof the invention, such as embodiments employing thin-film siliconprocesses, anode 302 and cathode 301 will be side-by-side in activelayer 103 rather than stacked vertically. The circuit branch comprisingthis diode has variable impedance based on the relative voltages of gate113 and body 109. In the situation where the potential of gate 113drops, the impedance of this variable impedance circuit branch will dropnearly to zero thereby latching body 109 to gate 113 when the gate islow.

Embodiments of the present invention which are described with referenceto FIG. 3 in the previous paragraph function to filter the benefits ofthe floating-body effect from the effect's drawbacks when active device203 is used in certain applications. These advantages are discussedabove with reference to prior art smart body contacts. As before withreference to FIG. 2, these benefits are achieved without having todisturb or alter the layout of active device 203. Therefore, the designof active device 203 can be altered to accommodate other concernsdecoupled from concerns regarding the floating-body effect. In addition,in specific embodiments of the invention the impedance of the variableimpedance circuit branch in its low impedance state can actually behigher than in some prior art body contacts and still retain efficacy.In embodiments of the present invention utilizing smart body contacts toprevent harmonic distortion of a signal passing above an off state RFswitch, the carriers that must be removed from the body are thosegenerated through much slower processes than those generated byavalanche breakdown and impact ionization. The relevant processes areseveral orders of magnitude slower and therefore the generated chargecan be removed even through a high impedance path. Therefore, thecircuitry that comprises the variable impedance path lying within theactive layer can be kept to a minimal size for a commensurately minimalimpact on the overall size and cost of a device using SOI structure 300.

A specific embodiment of the present invention can be described withreference again to FIG. 3. In FIG. 3, body contact 204 is ohmic andthere is negligible resistance from body contact 204 to second contact205. Also, second contact 205 is directly below the diode comprised ofcathode 301 and anode 302. Since active device 203 is an NFET the gatewill go high during its on state. Therefore, anode 302 will be at alower potential than cathode 301 and the diode will be reversed biased.This will prevent carriers from departing body 109 which will providethe NFET that is active device 203 to support a higher drive current andprevent forward bias of the body to source diode, which would cause highcurrents to flow in an undesired path. If active device 203 was a PFETthe gate would go low during its on state. Therefore, anode 302 andcathode 301 would need to be switched in FIG. 3. If this configurationwere applied, the diode would be reversed biased when the PFET was inits on state and the device 206 could support a higher drive current inits on state, and prevent forward bias of the body to source diode.Preventing forward bias of this diode is important to avoid the flow ofhigh currents in an undesired path.

In specific embodiments of the present invention, the same bias schemeis provided to body 109 as described with reference to FIG. 3 usingalternative structures. For example, an independent voltage bias sourcecan be applied to body 109 through electrically conductive layer 201.This voltage bias source would provide a variable voltage depending uponthe voltage on gate 113 to provide the same effect as described withreference to FIG. 3. As another example, a FET could be coupled in aspart of variable impedance path to serve a similar function to thatprovided by the diode in FIG. 3, that is, the FET will provide a lowimpedance path from the body to the gate when the transistor is not inan on state, and will provide a high impedance path from the body to thegate when the transistor is in an on state. In specific embodiments ofthe invention, various other circuits and configurations are applied forremoving the charge from body 109 in accordance with the conceptsillustrated by FIG. 3.

An SOI structure 400 that is in accordance with the present inventioncan be described with reference to FIG. 4. FIG. 4 is similar to FIG. 2with the exception that the circuit branch from second contact 205rising up into active layer 103 is a variable impedance path 401. Inspecific embodiments of the invention, body contact 204 is a hot-carrierdiode which provides for the variable aspect of variable impedance path401. In specific embodiments where active device 203 is an NFET device,the hot-carrier diode would be reversed-biased when the potential ongate 113 was high, and forward biased if the potential on gate 113 waslow. These embodiments will therefore exhibit the same characteristicsdescribed above with reference to smart body contacts. Advantageously,this configuration does not require any active devices to be built up inactive layer 201. This will therefore save space given that variableimpedance path 401 can be implemented using only a single metal linepassing through active layer 103.

In specific embodiments of the invention, the metal used to formelectrically conductive layer 201 is used for other purposes as well.For example, the metal may be used as assembly metal to provide contactsto the active layer. Such contacts could be used to provide powersignals into the active layer. The contacts could also be used to routesignal lines to and from the active layer. As another example, the metalcan be run along the channel on the backside of the SOI structure todecrease the capacitance between body and source and between body anddrain. The reason this configuration will reduce these parasiticcapacitances is the metallization will not cross over the source ordrain silicon and will instead remain over the channel or body area.Therefore the parallel plate capacitance between the body metal line andthe source and/or drain is minimized. This will produce advantageousresults given that the speed and performance of a device is inherentlylimited by the size of its parasitic capacitances.

A specific embodiment of the invention exhibiting large channel contactscan be described with reference to FIG. 5. FIG. 5 illustrates the backsurface of SOI structure 500. Lithographic resolution and alignmentcapabilities of a fabrication process may preclude the creation of acontact to be used as body contact 204 with a high rate of success. Acritical design failure would result if nearly any FET in a design wasfaced with a situation where its drain and source where shorted togetherby the electrically conductive material used for body contact 204. Inspecific embodiments of the invention, larger landing pads 501 ofchannel material can be made to increase the width of channel 502 at thechannel contact locations by an amount sufficient to allow contact tothe channel while ensuring that source or drain are not contacted. Asseen in FIG. 5, the metal deposited to form backside contact 503 to formbody contact 204 has a larger area to make contact with channel 502 atlanding pad 501 thereby reducing constraints upon the manufacturingprocess and potentially increasing fabrication yield. One method thatcan be used to create a larger landing pad 501 includes widening thepolysilicon gate in that shape. A second method that can be used tocreate a larger landing pad 501 includes altering the source and drainimplant layout in that shape while keeping the polysilicon shapeunchanged. Although these embodiments slightly work against theadvantages of the present invention in terms of decoupling the bodycontact architecture from the transistor architecture, the modificationwould generally only need to be slight and would be minimal compared toprior art approaches that deposited body contacts directly under oradjoining the device itself in the active layer.

Methods of producing an integrated circuit that are in accordance withthe present invention can be described with reference to FIG. 6. In step600 an SOI structure undergoes processing to form an active device in anactive layer of the SOI wafer. The circuitry formed during this step andin this layer can include but is not limited to technologies such asCMOS, BiCMOS, SiGe, GaAs, InGaAs, and GaN. The circuitry can comprise:various active devices such as diodes and transistors; various passivedevices such as resistors, capacitors, and inductors; and routingcircuitry such as metal wires and vias. Various photolithographic andchemical deposition steps can be conducted to formulate this circuitry.Step 600 includes the formation of a gate of the active device. Step 600may also include the formation of contacts in the active layer that aredisposed on the bottom of the active layer vertically adjacent to theinsulator layer. These contacts may be made of channel material in thechannel region of the active device. In specific embodiments of theinvention, contacts may be made of areas of channel material that arewider than the remainder of a channel formed by the material. Theselarger areas could form landing pads for later connection to contactsdeposited from the back of the active wafer as described above. Step 600could also include the formation of contact separate from the activedevice, and a circuit branch that connects to a separate contact formedon the bottom of the active layer. This circuit branch could thenconnect to the source or gate of the active device. This circuit branchcould be used to form part of a variable impedance path or generalconductive path as described with regard to the devices described above.Finally, step 600 can also include the step of forming a diode in theactive layer. This diode could then be used to form part of the variableimpedance path described with regard to the devices described above.This diode can be placed directly above a contact but it can be placedanywhere in the active layer. The diode should be formed so as to matchthe necessary polarity for the devices described above to functionproperly in accordance with the present invention.

The remaining steps of the method illustrated by FIG. 6 involve backsideprocessing. These steps may be preceded by the attachment of a temporaryhandle wafer to the top side of the SOI wafer. This wafer can providestability to the SOI wafer while the remaining steps are carried out.However, as mentioned previously the attachment of this wafer is notnecessary as support can be provided through other means. The handlewafer can have an insulator layer that bonds through various means tothe top of the SOI wafer. However, the handle wafer may also have alayer that bonds to the top of the SOI wafer that is comprised ofsemiconductor material or a conductive material. In step 601, back sideprocessing commences with the removal of the SOI wafer substrate. Thesubstrate could be removed using mechanical and chemical meansindependently or in combination. For example, mechanical grinding can beused to thin the substrate material from an original thickness ofapproximately 800 micro-meters (μm) to approximately 20 μm. If thesubstrate is silicon, the final thickness of substrate material may beremoved with a wet etch such as KOH or TMAH. The final thickness ofsubstrate material may also be removed using a dry plasma etch. Thesubstrate can be removed with a high precision or etch rate ratio. Theetch rate ratio refers to the ratio of the portion of desired substratematerial that was removed from the back of the wafer to the portion ofadditional material that was removed which should not have been removed.In specific embodiments of the invention, the insulator layer is aburied-oxide that acts as an etch stop since the etch rate ratio isextremely high for the removal of all the substrate up to the buriedoxide.

In specific embodiments of the invention, the removal of substratematerial in step 601 is followed by the deposition of dielectrics orpassivation layers. In specific embodiments of the invention, step 601can be followed by the deposition of passivation layers to prevent ioniccontamination of the SOI structure. Finally, in specific embodiments ofthe invention, step 601 can be followed by the deposition of dielectriclayers which have the added benefit of reducing coupling capacitancebetween active devices in the active layer and the back sideelectrically conductive layer by spacing the electrically conductivelayer away from the active devices.

In step 602, insulator material is removed from the back of the SOIwafer to form an excavated insulator region. In specific embodiments ofthe present invention, this excavated insulator region is located belowa body of an active device in the active layer, and a second portion ofthis excavated insulator region is located below a separate portion ofthe active layer. In specific embodiments of the present invention, theexcavated insulator region may be located underneath the preparedcontacts that may have been produced in step 600. In specificembodiments of the invention, the separate portion of the active layermay be where a diode that was produced in step 600 is located. Step 602may involve the removal of additional layers including passivationdielectric. In general, the pattern of insulator removal will allow forthe deposition of an electrically conductive layer in step 603 that willallow electrical contact between any of the individual portions of theexcavated insulator region. These patterns can be formed using standardphotolithographic techniques and wet or dry etches.

In step 603, an electrically conductive layer is disposed on the backside of the SOI wafer. This layer can be applied in a patterned fashionto allow for connection between isolated sets of portions of theexcavated insulator region. This electrically conductive layer willcouple the body of an active device in one portion of the excavatedinsulator region to a separate portion of the excavated insulatorregion. The deposition of this electrically conductive material can bedone using electron beam sputtering, electroplating, electrolessplating, selective chemical vapor deposition, and various other methods.In specific embodiments of the invention, step 603 can be accompanied bythe deposition of various other layers to provide improved thermalcharacteristics to the SOI structure. In specific embodiments of theinvention, step 603 can be accompanied by the deposition of multiplelayers in sequence providing barrier metal layers, anti-reflectioncoatings, and various other layers.

In specific embodiments of the invention, the electrically conductivematerial deposited in step 603 is patterned across the back of the SOIstructure. The electrically conductive material can be patterned to runparallel or perpendicular with the channel of an active device in theactive wafer. However, the electrically conductive material can bepatterned independently of the channel orientations as well. In thespecific embodiments where the electrically conductive material ispatterned to run parallel with the channel, the overall capacitance seenby the active device will be decreased.

In specific embodiments of the invention, the electrically conductivematerial deposited in step 603 forms a hot-carrier diode junctionbetween the active layer and the electrically conductive material at thebody contact. In situations where the active device is a NFET and thebody is thereby p-type, various materials can be used to create thisdevice. A nonexclusive list of metals that can be used includes,aluminum, titanium, gold, palladium, nickel, platinum, and cobalt. Ifthe device is a PFET and the body is thereby n-type, the samenonexclusive list includes, aluminum, platinum, chromium, gold, andhafnium. The benefits of the resulting configurations are describedabove. In order to reduce sheet resistance, a thin layer of the metalused to create the hot-carrier diode can first be deposited, followed bya layer of lower resistivity metal such as aluminum or copper.

In specific embodiments of the invention, the electrically conductivematerial deposited in step 603 is additionally used for assembly. Theelectrically conductive layer could comprise solder bumps, copper posts,or other types of packaging materials. This assembly metal could be usedto provide power to the circuit in the active layer of the SOIstructure, and could additionally route signals to and from the activelayer of the SOI structure. This assembly material could also bedisposed in a separate deposition after the electrically conductivelayer used to generate the body contact has already been deposited.

An SOI structure 700 that is in accordance with the present inventioncan be described with reference to FIG. 7. SOI structure 700 compriseselectrically conductive layer 201. Electrically conductive layer 201comprises a single contiguous region of material. Electricallyconductive layer 201 is at least partially vertically coextensive withinsulator layer 102 in excavated insulator region 202. Electricallyconductive layer 201 provides a low barrier contact to both body 109 andsource 111. Therefore, body 109 is tied to source 111 with a singlecontact. A structure in accordance with these embodiments can beproduced using methods described with reference to FIG. 6 with specificpatterns applied for substrate removal in step 601 to expose the bottomof source 111.

Specific embodiments of the invention that are in accordance with FIG. 7exhibit advantageous characteristics. With reference to FIG. 5, theseembodiments exhibit advantageous characteristics because the back sidecontact will naturally already have a larger landing pad to work withgiven that the single contact for electrically conductive layer 201 willbe disposed on both body 109 and source 111. In addition, in specificembodiments the tie does not take up any room in active layer 103because the tie exists solely within excavated insulator region 202. Inspecific applications, embodiments in accordance with FIG. 7 will beeasier to manufacture than other embodiments discussed above.

Although embodiments of the invention have been discussed primarily withrespect to specific embodiments thereof, other variations are possible.Various configurations of the described system may be used in place of,or in addition to, the configurations presented herein. For example,although the devices were discussed often with reference to siliconsubstrates and oxide insulator layers the invention will function withany form of semiconductor-on-insulator wafers, structures, or devices.For example, the invention will function in combination withsilicon-on-sapphire structures. In addition, the invention can functionor operate upon circuitry using any form of technology such as CMOS,bipolar, BiCMOS, SiGe, Ga, As, InGaAs, GaN and any other form ofsemiconductor technology or compound semiconductor technology. Inaddition, there may be additional layers of materials disposed betweenthose layers mentioned herein. Semiconductor processing is a highlydetailed field, and layers were only mentioned herein if they wereabsolutely necessary to describe the invention to avoid confusion. Forexample, there may be layers of passivation disposed on the active layerto prevent the circuitry from reacting with its environment. Inaddition, the use of the word “layer” such as when describing an activelayer or a insulator layer does not preclude such layers being comprisedof more than one material. For example, there may be layers of glass orsome other insulator below metal lines in active circuitry in additionto a silicon-dioxide insulator beneath the entire active layer of an SOIstructure. However, the term insulator layer can cover the entirestructure of the glass and silicon-dioxide insulator.

Those skilled in the art will appreciate that the foregoing descriptionis by way of example only, and is not intended to limit the invention.Nothing in the disclosure should indicate that the invention is limitedto systems that require a particular form of semiconductor processing orto integrated circuits. Functions may be performed by hardware orsoftware, as desired. In general, any diagrams presented are onlyintended to indicate one possible configuration, and many variations arepossible. Although the disclosure was focused on the application of theinvention to FET devices the invention will also help to alleviateparasitic issues for BJT devices in SOI architectures. Those skilled inthe art will also appreciate that methods and systems consistent withthe present invention are suitable for use in a wide range ofapplications encompassing any related to the accumulation of chargecarriers in a specific region of an electronic device.

As another embodiment, the current invention discloses a stacked-chipassembly and a method of stacking chips. The chip-stacking procedurepresented is simple and low-cost, can result in a thin and compactdesign, and is well suited to the integration ofsemiconductor-on-insulator integrated circuit chips. In embodiments ofthe present invention, methods are described in which the active andinsulating layers of a semiconductor-on-insulator is transferred to theback surface of any mechanically stable structure having active circuitson its front surface. This mechanically stable structure, or substrate,may be, for example, a bulk semiconductor device wafer, or anothersemiconductor-on-insulator. The substrate thus provides support for thevery thin active and insulating layers of thesemiconductor-on-insulator. This transfer process does not require theextra steps of transferring to a temporary carrier first, thenperforming a second bond and removing the temporary carrier.

This results the transferred active layer being interposed between thesubstrate and the transferred insulating layer. Therefore, electricalaccess to the active layer can be made by excavating the insulatinglayer and forming a metal contact, as described in steps 602 and 603 ofFIG. 6. This allows both layers of active circuitry to be accessedwithout the need for vertical connections between chips such asthrough-silicon vias. Vertical connections between chips often requireexpensive fine-accuracy alignment (<5 microns) of one chip to the other,since the vertical vias are often less than 5 microns in diameter, andspaced less than 5 microns apart. In the current invention, therefore,this expensive, highly accurate chip-to-chip alignment is not necessary.

In the current invention, either the semiconductor-on-insulator circuitor the circuit formed on the supporting substrate may be bonded to aprinted circuit board with solder bumps (the “flip chip” method) for aminimal chip outline area. The supporting substrate may be thinned,enabling a very thin board assembly—often necessary for a small, thinelectronic device.

FIG. 8 illustrates one embodiment of a method of the present disclosure,in which a semiconductor-on-insulator is transferred to the back of asubstrate having a second integrated circuit on its front side. Theresulting assembly is attached to a printed circuit board so as toelectrically connect both circuits to the board. In flowchart 2000 ofFIG. 8, a semiconductor-on-insulator including an insulating layer witha first surface and a second surface, a first active layer connected tothe first surface of the insulator, and a handle layer connected to thesecond surface of the insulator, is provided in step 2010. The firstactive layer may be formed, for example, by using a standardcomplementary metal-oxide-semiconductor (CMOS) fabrication process, orother processes as described in step 600 of FIG. 6. Such a process may,for example, form transistors, contacts, and interconnect layersconnected to form an integrated circuit.

In step 2020, a substrate with a first surface and a second surface isprovided. In step 2030, a second active layer is formed in the firstsurface of the substrate. The second active layer may also be formed,for example, by using a standard CMOS process, which would include, forexample, forming transistors, contacts, and interconnect layers. Thesubstrate may comprise a semiconductor, such as, for example, silicon orgermanium, or it may comprise an insulator, such as, for example,sapphire or quartz, or it may comprise any other type of material. Instep 2040, the substrate may be thinned. Material may be removed fromthe second surface of the substrate by, for example, mechanicalgrinding. In step 2050, the first active layer is coupled to the secondsurface of the second substrate. Any suitable coupling or bonding methodthat results in a permanent bond may be used; for example direct orfusion bonding, permanent adhesive bonding, metallic interdiffusion oreutectic bonding. Note that, in some embodiments, this step wouldinclude an alignment step, such that scribe lines on the silicon oninsulator and the substrate are roughly aligned to each other.

In step 2060, the handle layer of the semiconductor-on-insulator isremoved, as described in step 601 in FIG. 6; that is, using mechanicaland chemical means independently or in combination. In step 2070, afirst metal bond pad is formed on the second surface of the insulatorsuch that it is electrically connected to the first active layer.Techniques as described in steps 602 and 603 in FIG. 6 may be employedto form the first metal bond pad. These may include forming a viapattern on the insulator, using this pattern to etch via holes throughthe insulator to contact a layer of semiconductor or metal, anddepositing and patterning a layer of metal into the via hole. This layerof metal may form, alone or in combination with subsequently depositedmetal layers, the first bond pad. This pad may electrically connect toan input, output, power, ground, or some other node of the integratedcircuit provided in step 2010.

Still referring to FIG. 8, a second metal bond pad is formed on secondactive layer in step 2080. As described in step 2070, this pad mayelectrically connect to an input, output, power, ground, or some othernode of the integrated circuit formed in step 2030. Physically, this padmay connect to a metal interconnect layer formed as part of step 2030.In some embodiments, the formation of the second pad may take placebefore the bonding step 2050; for example, during the second activelayer formation (step 2030). In step 2090, a solder bump is formed onthe first metal bond pad on the first active layer. Prior to thisbumping step, the chips on each active layer may be tested. In step2100, the bonded assembly is optionally singluated into individualchips. This step may include, for example, dicing with a saw.

In step 2110 of FIG. 8, the solder bump is attached to a third metal padon a printed circuit board. This step may be accomplished, for example,by completing the solder step; that is, by melting the solder bump sothat it adheres to the material of the third metal pad on a printedcircuit board. In step 2120, the second metal bond pad on the secondactive layer is wire bonded to a fourth metal pad on the printed circuitboard. The resulting structure has two stacked integrated circuits, bothof which are electrically connected independently to a printed circuitboard.

FIGS. 9a-9i illustrate an exemplary stacked integrated circuitfabricated according to the method of FIG. 8. In FIG. 9a , asemiconductor-on-insulator 300 is provided, comprising an active layer303 and a handle layer 311, with an insulating layer 310 disposedbetween them. The insulating layer 310 has a surface 302 in contact withthe handle layer 311. The handle layer 311 may be, for example, asilicon wafer which may be 500 to 900 microns thick. The insulator 310may be, for example, silicon dioxide which may be 0.1 to 2 micronsthick. The active layer 303 may be, for example, a thin silicon layer inwhich transistors (comprising, for example, gate, source, drain and bodyregions), isolation areas, contacts, and interconnect layers may havebeen formed. The thin silicon layer may be, for example, 0.05 to 3microns thick. The active layer 303 may form a completed integratedcircuit. This active layer could be formed with techniques similar tothose described in step 600 of FIG. 6; that is, a CMOS or BiCMOSprocess, or a process that forms high-power devices or optoelectronicdevices in addition to MOS transistors. Semiconducting materials used inthis active layer formation may include, for example, Si, SiGe, GaAs,InGaAs, and GaN. This active layer may include, for example,semiconducting layers, isolation areas, contacts, insulating layers, andinterconnect layers, forming a complete integrated circuit. Thecircuitry can comprise: various active devices such as diodes andtransistors, various passive devices such as resistors, capacitors, andinductors. The active layer 303 may comprise a plurality of integratedcircuits, separated by scribe lines 308. The width of these scribe linesmay be, for example, 40 microns, or 80 microns.

In FIG. 9b , a substrate 350, having a first surface 351 and a secondsurface 352, is provided. This substrate may be, for example, a siliconwafer which is, for example, 500 to 900 microns thick. Alternatively,this substrate may comprise a different semiconductor, for example,germanium, gallium arsenide, or gallium nitride, or it may comprise aninsulator, for example, sapphire or quartz. In FIG. 9c , a second activelayer 353 is formed on the first substrate 350. The second active layer353 may be formed using any of the techniques described for use in theformation of the first active layer 303, for example, a CMOS process.The second active layer 353 may include any of the materials,structures, and circuit elements listed in the description of the firstactive layer 303; for example, silicon metal-oxide-semiconductortransistors, diodes, contacts, isolation areas, and interconnect.Similarly, the second active layer 353 may comprise a plurality ofintegrated circuits, separated by scribe lines 358. FIG. 9c also showsmetal bond pads 354 formed in the second active layer. These metal padsmay be made from any metal compatible with solder bumping or wirebonding; for example, copper or aluminum. The formation of the metalbond pads 354 in the second active layer 353 may also include theformation of a passivation layer, for example, silicon nitride orsilicon oxynitride, to prevent the circuitry from reacting with itsenvironment. Formation of the metal bond pads 354 would thus includeforming pad openings to access the bond pads 354.

In FIG. 9d , the first active layer 303 is coupled to the second surface352 of the substrate 350, forming the bonded integrated circuit assembly340. Prior to this step, the substrate 350 may be thinned, for example,to a final thickness of 150 microns, or 100 microns, or 80 microns, or50 microns, or 30 microns, or 10 microns. The thinning step may beinclude, for example, first attaching the substrate's first surface 351to an adhesive backgrind tape, or to a rigid handle wafer coated withadhesive. The substrate's second surface 352 then may undergo amechanical or chemical-mechanical grinding step, or a purely chemicalpolishing step, or any combination of these. The adhesive backgrind tapeor rigid handle wafer is then removed.

Prior to coupling the active layer 303 to the second surface 352 ofsubstrate 350, silicon-on-insulator 300 and substrate 350 may be alignedto each other, using, for example, infrared imaging. The purpose of thisalignment may be to align the scribe lines 308 and 358 on top of eachother. Thus, the accuracy required of this alignment step is dependentupon, for example, the width of the scribe lines 358 and 308; forexample, the alignment accuracy may be one fourth of the scribe linewidth, or 10 microns, or 20 microns. This is a less stringent accuracythan what is needed for, for example, aligning wafers that must havethrough-silicon via connections completed by the bonding. Suchalignments may require less than 1 micron of accuracy. Thus, embodimentsof the present invention may use less expensive equipment and processesfor bonding than what is required to form other integrated circuitassemblies.

The first active layer 303 and the second surface 352 of substrate 350are then coupled together. This process may use, for example, a bondingprocess. Any of a number of methods for bonding may be used, includingbut not limited to: direct or fusion bonding, permanent adhesive bonding(using, for example, benzocyclobutene or polyimide), or bonding usingmetallic interdiffusion or eutectic layers, such as copper, tin, orgold. These bonding techniques may take place under atmosphere, or in avacuum, at temperatures, for example, of less than 450 degrees Celsius(° C.), or less than 350° C., or less than 250° C., or at roomtemperature. Some bonding techniques, for example, metallicinterdiffusion bonding, require relatively high bonding pressures (forexample, 60 kilonewtons); others, for example, adhesive bonding orfusion bonding, require light bonding pressure (for example, less than 5Newtons). Some bonding methods, such as direct or fusion bonding, mayrequire a surface activation step, which may render each surfacehydrophilic, allowing a van der Waals bond to form. Such an activationstep may include a plasma treatment, a wet chemical treatment, or acombination of these. An annealing step at, for example, 400° C., may berequired to convert the van der Waals bond to a covalent bond. Note thatsome bonding techniques, for example, adhesive or metallicinterdiffusion bonding, require use of an intermediate layer (adhesiveor metal, for example), which remains in the assembly (not shown in FIG.9d ).

In FIG. 9e , the handle layer 311 is removed. This removal process maybe similar to that described in detail in the discussion of step 601 inFIG. 6. For example, mechanical grinding can be used to thin thesubstrate material from an original thickness of approximately 800microns (μm) to approximately 20 μm. If the substrate is silicon, thefinal thickness of substrate material may be removed with a wet etchsuch as potassium hydroxide (KOH) or tetramethylammonium hydroxide(TMAH). The final thickness of substrate material may also be removedusing a dry plasma etch. The final step of this process may include anetch that has a high semiconductor-to-insulator selectivity. Theselectivity refers to the ratio of the portion of desired substratematerial that was removed from the back of the wafer to the portion ofadditional material that was removed which should not have been removed.For example, 20 weight % TMAH in water at 79.8° C. etches silicondioxide only very slowly, and thus would provide a high selectivityetch. As described in the discussion of step 601 in FIG. 6, the removalof substrate material may be followed by the deposition of dielectricsor passivation layers to prevent ionic contamination of the SOIstructure.

Turning to FIG. 9f , bond pads 304 are formed on the second surface 302of insulating layer 310, electrically connecting to the first activelayer 303. The method to form this pad may proceed as described in steps602 and 603 of FIG. 6. In some embodiments, standard photolithographictechniques may be used to pattern and etch via holes in the insulatinglayer 310. These via holes may extend only through the insulating layer310, or they may extend into any layers beyond the insulating layer. Thevia holes may terminate, for example, on a semiconductor or interconnectlayer, or a filled contact that was previously formed during theformation of active layer 303. In some embodiments, depositedpassivation layers would also be etched during the via hole formationprocess. Metal layers may then be deposited into the via holes, usingstandard techniques such as, for example, sputtering or electroplating.The metal layers may comprise, for example, aluminum or copper, orcombinations of these. The metal layers may be patterned using standardpositive or negative-tone photolithographic techniques. The bond pads304 may be formed from these metal layers, or other metal layerssubsequently deposited and patterned.

In FIG. 9g , solder bumps 305 are applied to the metal pads 304connected to active layer 303. The solder bumps may be comprised of, forexample, lead, tin, copper, bismuth, silver, gallium, indium, or somecombination thereof. The solder bumps may be 500 microns in diameter, or100 microns in diameter, or 50 microns in diameter, or 25 microns indiameter, and they may be placed on 1 mm pitches, or 200 micron pitches,or 100 micron pitches, or 50 micron pitches. The solder bumps may beapplied by any of a number of processes; for example, by plating, screenprinting, evaporation, or transfer from a glass mold. Prior to attachingsolder bumps, the metal pads 304 may have additional metal layers, forexample, titanium, tin, tungsten, copper, or some combination thereof,deposited on them. Also, the integrated circuits formed in active layers303 and 353 may be electrically tested prior to attaching the solderbumps 305.

FIG. 9h shows two bonded integrated circuit assemblies 370 a and 370 b,formed by singulating the integrated circuit assembly 340 (FIG. 9g ).This singulation process may use any of a number of methods to dice thebonded pair of wafers, for example, a mechanical saw, a laser cut, or adry etch. The integrated circuit assemblies are separated along thescribe lines 308 and 358 (FIG. 9f ).

Turning to FIG. 9i , the bumped assembly 370 a is attached to a printedcircuit board 306, on which metal pads 307 and 357 have been formed.These pads may be comprised of, for example, copper or aluminum.Assembly 370 a is placed such that the solder bumps 305 are contactingmetal pads 307. The solder bumps are then melted to form an electricalconnection between pads 307 on printed circuit board 306, and pads 304on active layer 303. This melting can be performed by, for example,ultrasonic soldering or reflow soldering. The temperature required forthis melting may be, for example, about 250° C., or about 200° C., orabout 150° C. Underfilling of the bonded assembly 370 a, wherein adielectric layer (not shown) is inserted between the assembly 370 a andthe board 306, may also be performed.

Also shown in FIG. 9i is the connection of the metal pads 354 on thesecond active layer 353 to metal pads 357 on printed circuit board 306.This connection is made by use of wires 355. These wires may becomprised of, for example, aluminum, gold, or copper, which may bealloyed with, for example, beryllium or magnesium. To connect the wires355 to the pads 307 and 354, any of a number of wire bonding processesmay be used, including ball bonding or wedge bonding. The wires 355 arewelded to pads 307 and 354 using heat, ultrasonic energy, pressure, orsome combination thereof.

In FIG. 10, an alternative assembled structure is shown. In thisstructure, the first active layer 303 of integrated circuit assembly 370a may be electrically connected to active layer 303 of a secondintegrated circuit assembly 370 b, instead of being connected to theprinted circuit board 306. Such a connection may be established, forexample, by wire bonding the pads 354 on assemblies 370 a and 370 b toeach other using wire 309.

In FIGS. 11a-b , another alternative embodiment of an assembledstructure is described. FIG. 11a shows a single integrated circuitassembly 370 a with solder bumps 315 and 305 applied to the metal pads354 and 304, respectively. In FIG. 4b , the bumped assembly 370 a isattached to printed circuit boards 306 and 316, on which metal pads 307and 357, respectively, have been formed. Assembly 370 a is placed suchthat the solder bumps 305 are contacting metal pads 307, and the solderbumps 355 are contacting metal pads 357. The solder bumps are thenmelted to form electrical connections between pads 307 on printedcircuit board 306 and pads 304 on active layer 303, as well as betweenpads 357 on printed circuit board 316 and pads 354 on active layer 353.This melting can be performed by, for example, ultrasonic soldering orreflow soldering.

In FIGS. 12a-b , yet another alternative embodiment of an assembledstructure according to the present invention is described. In thisembodiment, three integrated circuits are stacked on top of each otherand attached to a printed circuit board, in such a way as to provide allcircuit elements in each of the three integrated circuits an electricalpath to the printed circuit board. In FIG. 12a , solder bumps 315 areapplied to some, but not all, of metal pads 354 of a single integratedcircuit assembly 370 a, in addition to the solder bumps 305 that areapplied to pads 304. FIG. 12b shows a third substrate 260 having a firstsurface 261, a second surface 262, and an active layer 263 formed on thefirst surface 261. Pad 264 is formed in active layer 263. Thirdsubstrate 260 is placed such that pad 264 is contacting solder bump 315.FIG. 12b also shows a printed circuit board 306 having pads 307 and 357.Assembly 370 a is placed such that the solder bumps 305 are contactingmetal pads 307. The solder bumps are then melted to form electricalconnections between pads 307 on printed circuit board 306 and pads 304on active layer 303, as well as between pads 264 on substrate 260 andsome of pads 354 on active layer 353. Finally, FIG. 12b also shows awire 355 connecting other pads 354 to pads 357 on printed circuit board.In this way, circuit elements in the active layer 263 may have anelectrical path to the printed circuit board 306 through circuitelements in active layer 353.

While the specification has been described in detail with respect tospecific embodiments of the invention, it will be appreciated that thoseskilled in the art, upon attaining an understanding of the foregoing,may readily conceive of alterations to, variations of, and equivalentsto these embodiments. These and other modifications and variations tothe present invention may be practiced by those skilled in the art,without departing from the spirit and scope of the present invention,which is more particularly set forth in the appended claims.

1. An integrated circuit assembly comprising: an insulating layer havinga first surface and a second surface; a first active layer contactingthe first surface of the insulating layer; a metal bond pad formed onthe second surface of the insulating layer; wherein the metal bond padis electrically coupled to the first active layer; a substrate having afirst surface and a second surface, the first active layer being coupledto the second surface of the substrate; a second active layer formed onthe first surface of the substrate; a first singulated wafer portionincluding the insulating layer and the first active layer; and a secondsingulated wafer portion bonded to the first singulated wafer portion,the second wafer singulated portion including the substrate and thesecond active layer.
 2. The integrated circuit assembly of claim 1,further comprising: a printed circuit board, the printed circuit boardbeing electrically coupled to the metal bond pad.
 3. The integratedcircuit assembly of claim 2, wherein the printed circuit board iselectrically coupled with a solder bump to the first active layer. 4.The integrated circuit assembly of claim 2, wherein the printed circuitboard is electrically coupled to the second active layer through a wirebond.
 5. The assembly of claim 2, wherein the printed circuit board iselectrically coupled with a solder bump to the second active layer. 6.The assembly of claim 2, wherein the printed circuit board iselectrically coupled to the first layer through a wire bond.
 7. Theintegrated circuit assembly of claim 1, wherein the substrate is lessthan 100 microns thick.
 8. The integrated circuit assembly of claim 1,wherein the substrate is less than 30 microns thick.
 9. The integratedcircuit assembly of claim 1, wherein the integrated circuit assemblydoes not include a vertical electrical connection through the firstsingulated wafer portion and the second singulated wafer portion. 10.The integrated circuit assembly of claim 1, wherein the first activelayer or the second active layer includes passive devices.
 11. Asingulated integrated circuit assembly comprising: a silicon oninsulator (SOI) wafer portion including a first active layer formed ontop of an insulating layer, the SOI wafer portion further including afirst plurality of metal bond pads on a back side of the insulatinglayer, each of the metal bond pads of the first plurality of metal bondpads being in communication with active devices of the first activelayer; and a first wafer portion having a second active layer formed ontop of a semiconductor substrate layer, the first wafer portion furtherincluding a second plurality of metal bond pads formed above the secondactive layer and being in communication with active devices of thesecond active layer, further wherein a back side of the first waferportion is bonded to a top side of the SOI wafer portion.
 12. Thesingulated integrated circuit assembly of claim 11, further comprising:a plurality of solder bumps disposed on the first plurality of metalbond pads; and a printed circuit board having a third plurality of metalbond pads in communication with the plurality of solder bumps.
 13. Thesingulated integrated circuit assembly of claim 11, further comprising:a plurality of solder bumps disposed on the second plurality of metalbond pads; and a printed circuit board having a third plurality of metalbond pads in communication with the plurality of solder bumps.
 14. Thesingulated integrated circuit assembly of claim 11, further comprising:a first printed circuit board coupled with the first plurality of metalbond pads; and a plurality of bonding wires coupling the secondplurality of metal bond pads to the first printed circuit board.
 15. Thesingulated integrated circuit assembly of claim 11, further comprising:a first printed circuit board coupled with the second plurality of metalbond pads; and a plurality of bonding wires coupling the first pluralityof metal bond pads to the first printed circuit board.
 16. A singulatedintegrated circuit assembly comprising: a first wafer portion having afirst active layer formed on top of a semiconductor substrate, the firstwafer portion further including a first metal bond pad formed on a topside of the first wafer portion and coupled with a first active deviceof the first active layer; and a second wafer portion having a secondactive layer formed on a top side of an insulator layer and having asecond metal bond pad formed on a back side of the insulator layer, thesecond bond pad being in electrical communication with a second activedevice of the second active layer, further wherein a top side of thesecond wafer portion is bonded to a back side of the first waferportion.
 17. The singulated integrated circuit assembly of claim 11,further comprising: a solder bump disposed on the first metal bond pad;and a printed circuit board having a third metal bond pad incommunication with the solder bump.
 18. The singulated integratedcircuit assembly of claim 11, further comprising: a solder bump disposedon the second metal bond pad; and a printed circuit board having a thirdmetal bond pad in communication with the solder bump.
 19. The singulatedintegrated circuit assembly of claim 11, further comprising: a firstprinted circuit board coupled with the first metal bond pad; and abonding wire coupling the second metal bond pad to the first printedcircuit board.
 20. The singulated integrated circuit assembly of claim11, further comprising: a first printed circuit board coupled with thesecond metal bond pad; and a bonding wire coupling the first metal bondpad to the first printed circuit board.